Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, etching, implanting, annealing, planarizing and so on.
Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
It is common to manufacture integrated circuits on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. These conductive regions are typically referred to as pads. In testing, these pads are commonly contacted with a probe card. Unfortunately, the dimensions, or area, of pads have been decreasing which makes contacting such pads with a conventional probe card difficult and time consuming.
What is needed are lower-cost, less-complex apparatus and methods to increase the efficiency of operations associated with testing the integrated circuits of a wafer.